1. Technical Field
The disclosure relates generally to fabrication of gate structure during formation of a semiconductor structure in complementary metal oxide semiconductor (CMOS) circuits, and more particularly, to methods of forming a dual high dielectric constant (high-k) front-end-of-the-line (FEOL) metal gate using photoresist mask.
2. Related Art
In the current state of the art, patterning of high-k dielectrics uses photoresist as a soft mask in place of hard mask techniques because silicon oxide (SiO2) or silicon nitride (Si2N3) interact/react with high-k dielectrics changing the properties of the high-k dielectrics for the fabrication of semiconductor structures in CMOS circuits. Photoresist for patterning of high-k materials is removed using organic solvents in view of the sensitivity of the patterned high-k dielectric materials to standard wet processes.
However, photoresist removal by organic solvents/chemicals is usually incomplete leaving residual carbon on the surface of high-k dielectric films on the substrate. Incomplete removal of photoresist may affect the fabrication of subsequent layers on the patterned high-k dielectrics and consequently the performance of the gate structure fabricated therefrom. For example, unremoved residual photoresist on high-k dielectric may cause the threshold voltage (Vt) to shift by more than 200 mv and the inversion thickness (Tinv) to increase by more than 2 A. Therefore, there is a need to completely remove any residual photoresist. Current techniques used in front-end-of-line (FEOL) fabrication of gate structures include wet chemical etching using sulfuric peroxide with or without the addition of oxygen plasma resist strip.